Field of the Invention
This invention relates generally to the field of computer processors. More particularly, the invention relates to a method and apparatus for multi-bit error detection and correction.
Description of the Related Art
Trapping and de-trapping of charges causes significant Vcc_min fluctuation in static on-chip memories such as static random access memories (SRAMs). By definition, if Vcc_min becomes larger than the supply voltage, and if the bit is accessed (either read or written), the bit can be flipped. This error event is commonly known as a “soft” error (i.e., the cell becomes normal again after some random time). Chip-level soft errors may occur when radioactive atoms of the chip release alpha particles. Because an alpha particle contains a charge and energy, the particle may hit a memory cell and cause the cell to change state to a different value.
Soft Error Rate (SER) is an important design target for high performance computing. Many techniques are used in products in order to hit SER requirements. One most widely used techniques for array structures is error correction code (ECC). Single Error Correction and Double Error Detection (SECDED) is one particular solution.
As technology scales, a single particle strike has a larger footprint in terms of storage cells, resulting in multiple bit flips. To counter this increasingly likely cause of multi-bit errors, double- or even triple-bit correction will become commonplace. Unfortunately, the cost of double- or triple-bit correction is typically double or triple that of single-bit correction in terms of extra storage and power.